1. Field of the Invention
The invention relates to the field of semiconductor processing and more particularly to a process of forming a thin gate dielectric for an MOS transistor.
2. Description of the Relevant Art
The basic MOS transistor is a well known electronic device which typically includes four terminals: the gate, source, drain, and substrate. The substrate terminal of n-channel MOS transistor is typically biased to the most negative voltage that the device is likely to encounter during circuit operation to prevent forward biasing of pn junctions formed within the substrate during circuit fabrication. In the most common MOS transistor configuration, the gate terminal functions as the device input by dictating the absence or presence of a conductive path between the source and drain terminals. When the gate voltage exceeds the source voltage by a threshold value (V.sub.T), current can flow freely from source to drain (or from drain to source) upon application of a potential difference between the two output terminals. When an MOS transistor is biased in a saturated condition (i.e., V.sub.gs .gtoreq.V.sub.T and V.sub.ds .gtoreq.V.sub.gs), the drain current i.sub.ds is, to a first order approximation, independent of the drain voltage. The current that flows under such conditions is referred to as the saturated drain current, I.sub.dsat. I.sub.dsat is typically calculated by biasing the gate and drain to a maximum operating voltage (e.g., 3 V), grounding the source and substrate terminals, and measuring the current i.sub.ds flowing between the source and drain terminals. I.sub.dsat is an indicator of the potential speed of an integrated circuit and is an important process parameter and, thus, maximizing I.sub.dsat is a desirable goal in any process design. A useful estimate of I.sub.dsat is provided by the expression: EQU I.sub.dsat .apprxeq.1/2 (W/L).mu..sub.n C.sub.ox (V.sub.DS).sup.2
where W/L is the ratio of the transistor channel width to length, .mu..sub.n is the carrier mobility, C.sub.ox is the capacitance per unit area of the gate dielectric structure, and V.sub.DS is the potential difference between the source and drain terminals. The equation reveals that I.sub.dsat varies proportionally with the capacitance per unit area C.sub.ox where C.sub.ox =.di-elect cons..sub.i /t.sub.ox, .di-elect cons..sub.i is the permittivity of the gate dielectric material and t.sub.ox is the dielectric thickness. From these equations it is apparent that reducing the gate oxide thickness t.sub.ox increases a saturated drain current I.sub.dsat. Because it is typically desirable to increase the saturated drain current I.sub.dsat, it is frequently desirable and necessary to reduce the thickness t.sub.ox of the gate dielectric.
Reducing the gate oxide thickness is conventionally accomplished by simply reducing the time of the thermal oxidation process. This method of reducing gate oxide thickness may be sufficient in applications where the gate oxide thickness is in excess of approximately 50 angstroms but becomes ineffective for extremely thin gate oxides (i.e., gate oxides less than 50 angstroms in thickness). For ultra thin gate oxides, the gate oxidation rate for the typical thermal process used to form the gate oxide is too great to achieve adequate control over variations in gate oxide thickness from run to run.
In addition, the typical gate oxide consists of a silicon-oxide composite such as thermal silicon dioxide which has a dielectric constant in the range of approximately 3.8 to 3.9. In ultra thin oxide applications, this dielectric constant, which directly affects the capacitance per unit area of the gate dielectric, is insufficient to ensure an adequate saturated drain current. Moreover, the silicon-oxide composite is typically insufficient as a barrier dielectric against mobile impurities that are frequently found in the conductive gate structures of semiconductor transistors. The problem of migrating mobile impurities is typically greatest in ultra thin oxide applications in which the conductive gate structure includes highly mobile impurities such as boron. Boron and other impurities from within the gate structure can migrate across the thin gate oxide and come to rest in the active area of the transistor channel region thereby inadvertently and undesirably altering the threshold voltage of the device.
It is therefore desirable to implement a process that is capable of producing ultra thin oxides with adequate control over the oxide thickness variation from run to run and that may result in an increased gate oxide capacitance per unit area while simultaneously reducing or eliminating the occurrence of mobile carriers and other impurities migrating across the gate dielectric structure.